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preliminary gs8160z18/36dgt-xxxv 18mb pipelined and flow through synchronous nbt srams 333 mhz ? 150 mhz 1.8 v or 2.5 v v dd 1.8 v or 2.5 v i/o 100-pin tqfp commercial temp industrial temp rev: 1.00 5/2011 1/22 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? 1.8 v or 2.5 v core power supply ? 1.8 v or 2.5 v i/o supply ? user-configurable pipeline and flow through mode ? lbo pin for linear or interleave burst mode ? pin compatible with 2mb, 4mb, 8mb, 36mb, 72mb and 144mb devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? zz pin for automatic power-down ? rohs-compliant 100-lead tqfp package available functional description the gs8160z18/36dgt-xxxv is an 18mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double la te write or flow through read/ single late write srams, allow u tilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched fr om read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/ write control inputs are ca ptured on the rising edge of the input clock. burst order control (lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and outp ut enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's out put drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs8160z18/36dgt-xxxv may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers th at capture input signals, the device incorporates a rising-edge-triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output dr ivers at the next rising edge of clock. parameter synopsis -333 -250 -200 -150 unit pipeline 3-1-1-1 t kq tcycle 3.0 3.0 3.0 4.0 3.0 5.0 3.8 6.7 ns ns curr (x18) curr (x36 tbd tbd tbd tbd tbd tbd tbd tbd ma ma flow through 2-1-1-1 t kq tcycle 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns curr (x18) curr (x36) tbd tbd tbd tbd tbd tbd tbd tbd ma ma
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 2/22 ? 2011, gsi technology gs8160z18dgt-xxxv pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b ft v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck w cke v dd v ss g adv a a a a a 1m x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 3/22 ? 2011, gsi technology gs8160z36dgt-xxxv pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck w cke v dd v ss g adv a a a a a 512k x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 4/22 ? 2011, gsi technology 100-pin tqfp pin descriptions symbol type description a 0 , a 1 in burst address inputs; preload the burst counter a in address inputs ck in clock input signal b a in byte write signal for data inputs dq a1 -dq a9 ; active low b b in byte write signal for data inputs dq b1 -dq b9 ; active low b c in byte write signal for data inputs dq c1 -dq c9 ; active low b d in byte write signal for data inputs dq d1 -dq d9 ; active low w in write enable; active low e 1 in chip enable; active low e 2 in chip enable; active high. for self decoded depth expansion e 3 in chip enable; active low. for self decoded depth expansion g in output enable; active low adv in advance/load ; burst address counter control pin cke in clock input buffer enable; active low dq a i/o byte a data input and output pins dq b i/o byte b data input and output pins dq c i/o byte c data input and output pins dq d i/o byte d data input and output pins zz in power down control; active high ft in pipeline/flow through mode control; active low lbo in linear burst order; active low v dd in core power supply v ss in ground v ddq in output driver power supply nc ? no connect
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 5/22 ? 2011, gsi technology gs8160z18/36dgt-xxxv nbt sram functional block diagram k sa1 sa0 burst counter lbo adv memory array e 3 e 2 e 1 g w b d b c b b b a ck cke d q ft dqa ? dqn k sa1? sa0? d q match write address register 2 write address register 1 write data register 2 write data register 1 k k k k k k sense amps write drivers read, write and data coherency control logic ft a 0 ?an
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 6/22 ? 2011, gsi technology functional details clocking deassertion of the clock enable (cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operati ons must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs (e 1 , e 2 and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables (e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contr ol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is sel ected, cke is active, and the write input is sampled low at the rising edge of clock. the byte write enable inputs (b a , b b , b c, & b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching the write command versus data pipe line length (2 cycles) to the read comman d versus data pipeline length (2 cycles). a t the first rising edge of clock, enable, writ e, byte write(s), and address are registered . the data in associated with that addr ess is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to op erations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in th at the write pipeline is one cy cle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second risin g edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop lhhhh
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 7/22 ? 2011, gsi technology synchronous truth table operation type address ck cke adv w bx e 1 e 2 e 3 g zz dq notes read cycle, begin burst r external l-h l l h x l h l l l q read cycle, continue burst b next l-h l h xxxxxll q 1,10 nop/read, begin burst r external l-h l l h x l h l h l high-z 2 dummy read, continue burst b next l-h l h x x x x x h l high-z 1,2,10 write cycle, begin burst w external l-h l l l l l h l x l d 3 write abort, begin burst d none l-h l l l h l h l x l high-z 1 write cycle, continue burst b next l-h l h xlxxxxl d 1,3,10 write abort, continue burst b next l-h l h x h x x x x l high-z 1,2,3,10 deselect cycle, power down d none l-h l l x x h x x x l high-z deselect cycle, power down d none l-h l l x x x x h x l high-z deselect cycle, power down d none l-h l l x x x l x x l high-z deselect cycle, continue d none l-h l h x x x x x x l high-z 1 sleep mode none x x x x x x x x x h high-z clock edge ignore, stall current l-h h x x x x x x x l - 4 notes: 1. continue burst cycles, whether read or wr ite, use the same control inputs. a deselect continue cycle can only be entered into if a deselect cycle is executed first. 2. dummy read and write abort can be consider ed nops because the sram performs no operat ion. a write abort occurs when the w pin is sampled low but no byte write pins are ac tive so no write operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles.
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 8/22 ? 2011, gsi technology pipeline and fl ow through read write control state diagram deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d current state (n) next state (n+1) transition ? input command code key notes: 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes ,as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline and flow through read/write control state diagram w r
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 9/22 ? 2011, gsi technology pipeline mode data i/o state diagram intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes: 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 10/22 ? 2011, gsi technology flow through mode data i/o state diagram high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes as indicated in the truth tables. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipeline and flow th rough read write c ontrol state diagram
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 11/22 ? 2011, gsi technology burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-t o-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded into the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin (lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst se quence is selected. see the tab les below for details. note: there is a pull-up device on the ft pin and a pull-down device on the zz pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft lflow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 12/22 ? 2011, gsi technology sleep mode during normal operation, zz must be pulled low, either by the user or by it?s intern al pull down resistor. when zz is pulled hi gh, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after 2 cycles of wake up time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exiting sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sl eep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on pin 14. not all vendors offer this option, however most mark pin 14 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. tzzr tzzh tzzs tkl tkl tkh tkh tkc tkc ck zz
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 13/22 ? 2011, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage on v ddq pins ? 0.5 to v dd v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( ? 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( ? 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c power supply voltage rang es (1.8 v/2.5 v version) parameter symbol min. typ. max. unit 1.8 v supply voltage v dd1 1.7 1.8 2.0 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 1.8 v v ddq i/o supply voltage v ddq1 1.7 1.8 v dd v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 v dd v v ddq2 & v ddq1 range logic levels parameter symbol min. typ. max. unit v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v v dd input low voltage v il ? 0.3 ? 0.3*v dd v note: unless otherwise noted, all performance s pecifications quoted are evaluated for worst case in the temperature range marked on t he device.
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 14/22 ? 2011, gsi technology note: these parameters are sample tested. operating temperature parameter symbol min. typ. max. unit junction temperature (commercial range versions) t j 02585 ? c junction temperature (industrial range versions)* t j ?40 25 100 ? c note: * the part numbers of industrial temperature range versions end with the character ?i?. unless otherwise noted, all performanc e specifications quoted are evaluated for worst case in the temperature range marked on the device. thermal impedance package test pcb substrate ?? ja (c/w) airflow = 0 m/s ? ja (c/w) airflow = 1 m/s ? ja (c/w) airflow = 2 m/s ?? jb (c/w) ? jc (c/w) 100 tqfp 4-layer 21.1 16.6 15.2 9.1 2.6 notes: 1. thermal impedance data is based on a number of samples from mulitple lots and should be viewed as a typical number. 2. the characteristics of the test fixtur e pcb influence reported thermal characterist ics of the device. be advised that a good thermal path to the pcb can result in cooling or heati ng of the ram depending on pcb temperature. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 810pf input/output capacitance c i/o v out = 0 v 12 14 pf 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd + 2.0 v 50% v dd v il note: input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 15/22 ? 2011, gsi technology ac test conditions parameter conditions figure 1 input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua ft input current i in v dd ? v in ? 0 v ? 100 ua 100 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua 1.8 v output high voltage v oh1 i oh = ? 4 ma, v ddq = 1.7 v v ddq ? 0.4 v ? 2.5 v output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? 1.8 v output low voltage v ol1 i ol = 4 ma ? 0.4 v 2.5 v output low voltage v ol2 i ol = 8 ma ? 0.4 v dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 16/22 ? 2011, gsi technology notes: 1. i dd and i ddq apply to any combination of v dd and v ddq operation. 2. all parameters listed are worst case scenario. operating currents parameter test conditions mode symbol -333 -250 -200 -150 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current device selected; all other inputs ? v ih o r ?? v il output open (x32/ x36) pipeline i dd i ddq tbd tbd tbd tbd tbd tbd tbd tbd ma flow through i dd i ddq tbd tbd tbd tbd tbd tbd tbd tbd ma (x18) pipeline i dd i ddq tbd tbd tbd tbd tbd tbd tbd tbd ma flow through i dd i ddq tbd tbd tbd tbd tbd tbd tbd tbd ma standby current zz ?? v dd ? 0.2 v ? pipeline i sb tbd tbd tbd tbd tbd tbd tbd tbd ma flow through i sb tbd tbd tbd tbd tbd tbd tbd tbd ma deselect current device deselected; all other inputs ?? v ih or ? v il ? pipeline i dd tbd tbd tbd tbd tbd tbd tbd tbd ma flow through i dd tbd tbd tbd tbd tbd tbd tbd tbd ma
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 17/22 ? 2011, gsi technology notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above. ac electrical characteristics parameter symbol -333 -250 -200 -150 unit min max min max min max min max pipeline clock cycle time tkc 3.0 ? 4.0 ? 5.0 ? 6.7 ? ns clock to output valid tkq ? 3.0 ? 3.0 ? 3.0 ? 3.8 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.0 ? 1.2 ? 1.4 ? 1.5 ? ns hold time th 0.1 ? 0.2 ? 0.4 ? 0.5 ? ns flow through clock cycle time tkc 5.0 ? 5.5 ? 6.5 ? 7.5 ? ns clock to output valid tkq ? 5.0 ? 5.5 ? 6.5 ? 7.5 ns clock to output invalid tkqx 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns clock to output in low-z tlz 1 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns setup time ts 1.3 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.0 ? 1.3 ? 1.3 ? 1.5 ? ns clock low time tkl 1.2 ? 1.5 ? 1.5 ? 1.7 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.8 ns g to output valid toe ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 18/22 ? 2011, gsi technology pi peline mode timing (nbt) write a read b suspend read c write d write no-op read e deselect thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd e d(a) d(d) q(e) q(b) q(c) ck a cke e * adv w bn dq
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 19/22 ? 2011, gsi technology fl ow through mode timing (nbt) write a write b write b+1 read c cont read d write e read f write g d(a) d(b) d(b+1) q(c) q(d) d(e) q(f) d(g) tolz toe tohz tkqx tkq tlz thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab c defg *note: e = high(false) if e1 = 1 or e2 = 0 or e3 = 1 ck cke e adv w bn a0?an dq g
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 20/22 ? 2011, gsi technology tqfp package drawi ng (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y ? notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 ? lead angle 0 ? ? 7 ?
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 21/22 ? 2011, gsi technology ordering information?gsi nbt synchronous sram org part number 1 type voltage option package speed 2 (mhz/ns) t a 3 1m x 18 gs8160z18dgt-333v nbt 1.8 v or 2.5 v rohs-compliant tqfp 333/5.0 c 1m x 18 gs8160z18dgt-250v nbt 1.8 v or 2.5 v rohs-compliant tqfp 250/5.5 c 1m x 18 gs8160z18dgt-200v nbt 1.8 v or 2.5 v rohs-compliant tqfp 200/6.5 c 1m x 18 gs8160z18dgt-150v nbt 1.8 v or 2.5 v rohs-compliant tqfp 150/7.5 c 512k x 36 gs8160z36dgt-333v nbt 1.8 v or 2.5 v rohs-compliant tqfp 333/5.0 c 512k x 36 gs8160z36dgt-250v nbt 1.8 v or 2.5 v rohs-compliant tqfp 250/5.5 c 512k x 36 gs8160z36dgt-200v nbt 1.8 v or 2.5 v rohs-compliant tqfp 200/6.5 c 512k x 36 gs8160z36dgt-150v nbt 1.8 v or 2.5 v rohs-compliant tqfp 150/7.5 c 1m x 18 gs8160z18dgt-333iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 333/5.0 i 1m x 18 gs8160z18dgt-250iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 250/5.5 i 1m x 18 gs8160z18dgt-200iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 200/6.5 i 1m x 18 gs8160z18dgt-150iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 150/7.5 i 512k x 36 gs8160z18dgt-333iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 333/5.0 i 512k x 36 gs8160z18dgt-250iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 250/5.5 i 512k x 36 gs8160z18dgt-200iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 200/6.5 i 512k x 36 gs8160z18dgt-150iv nbt 1.8 v or 2.5 v rohs-compliant tqfp 150/7.5 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs8160z36dgt-150ivt. 2. the speed column indicates the cycle fr equency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode . each device is pipeline/flow through mode-selectable by the user. 3. c = commercial temperature range. i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings
gs8160z18/36dgt-xxxv preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 5/2011 22/22 ? 2011, gsi technology 18mb sync sram datasheet revision history file name types of changes format or content description of changes 8160zxxd_v_r1 ? creation of new datasheet

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